Intel Pentium Processor – It is the microprocessor that performs many operations to run the computer process. It’s very important for the system process on the computer.
Intel is the main microprocessor company for developing a processor.
This is a technical topic. So, some knowledge may help peoples to understand how the processor does work.
AMD Processor VS Intel
Intel Processor – intel is the main company for the processor. Today, we know that I3, I5, I7, I9 processor have more popular.
Most people used Intel processor for handling large files like programming. The Intel processor is very costly. Because there are used many features.
AMD Processor – AMD is also an important inbuilt processor company.
Most people used the AMD processor for small files like used for word files or PowerPoint files. where the AMD processor is cheap than Intel. Because there are used fewer features.
But, My experience with AMD has different, I’m personally used AMD (A8-7410) with 2.5 GHz speed and that cost compare to the I3 processor has much low and I3 processor have the same speed. However, It’s much costly.
INTEL PENTIUM PROCESSOR
The Intel Pentium Processor is a 32-bit, superscalar architecture processor with a 64 – bit bus. At some stages inside the chip, it has a 256 – bit bus and has the ability to run almost two instructions per clock cycle.
It has some critical and frequently used instructions hardwired rather than micro-coded which accounts for the CISC-RISC design.
It employs superscalar integer pipelines, branch prediction, and highly pipelined floating-point until to achieve the highest x86 performance level.
While preserving the binary code compatibility with x86 architecture through it was the first one to break the x86 design philosophy (CISC).
The overall organization of the Intel Pentium microprocessor is shown in fig. It has a core execution unit, two integer pipelines, a floating-point pipeline with a dedicated adder, multiplier, and divider.
The separate on-chip instruction code and data caches meet the memory demands of the execution units, with a branch target buffer augmenting the instruction cache for dynamic branch prediction.
The external interface includes separate addresses and a 64 – bit data bus.
The integer pipeline of the Intel Pentium processor is simple as compared to the 80486 central processing unit. The pipeline has five stages (prefetch, first decode, the second decode, execute, and write back) with the following functions.
Prefetch (PF): – The prefetch stage prefetches (reading in advance) code from the instruction cache and aligns the code.
First Decode (D1): – In this stage, the CPU decodes the instruction to generate a control word. A single control word executes directly, while the complex instruction requires micro coded control sequence.
Second Decode (D2): – The CPU decodes the control word from the D1 stage for the use of nine the execute stage. In addition, the CPU generates addresses for data reference in the memory.
Execute (E): – The CPU either accesses the data cache or computers the result in the arithmetic and logic unit (ALU) in this stage.
Write Back (WB): – In the last stage, the CPU updates the registers and flags with the instruction results. All exceptions (triggered by some failure, e.g divide by zero) conditions must be resolved before instruction can advance to the WB stage.
Compared with the integer pipeline of the 80486 CPU, the Intel Pentium processor integrates the additional hardware in several instructions. For example, the 80486 CPU requires two clock cycles to decode several instructions.
But the Pentium takes one clock cycle and executes shift the superscale execution (executing more than one instruction at a time) branch prediction, and cache organization.
Super – Scalar Execution – The Intel Pentium Processor CPU has a superscalar organization that enables two instructions to execute in parallel. The ALU functions have been replicated in independent pipelines, called U and V (the pipeline names U and V neither of them were the initials of a functional unit in design partitioning).
In the prefetch (PF) and D1 stages described above, the CPU can fetch the decode two instructions in parallel and issue them to the U and V pipelines. The U and V have separate ALUs.
Additionally, for complex instructions, the CPU in D1 can generate microcode sequences that control both the U and V pipelines.
When a jump instruction is issued to the U pipeline, The CPU in D1 never issues any instruction to the V-pipe, thereby eliminating control dependencies.
The instruction issue algorithm takes control dependency into consideration and issues the instruction as per the algorithm listed below.
Several techniques are used to resolve dependencies between the instructions that might be executed in parallel. Various dependencies associated with the instruction are a resource, data, control, and duplication.
Resource Dependency: It occurs when two instructions require a signal from the functional unit or a data unit.
Data Dependency: It comes when one instruction writes the result that is read or written by another instruction. Consider an example that illustrates this concept.
I1 : MOV AX, BX # move data from BX location to AX
I2: MOV DX, AX #move data from AX location to DX
The instructions I1 and I2 cannot be executed in parallel because the result generated by I1 which is in AX registers is referred to as a source operand in the instruction I2. Hence, I1 and I2 cannot be executed in parallel.
Control Dependency: It occurs when the result of one instruction determines whether another instruction has to be executed or not.
if (condition) then
I1 : a <– 100
I2 : a <– 200
The instruction I1 and I2 cannot be executed in parallel because they have to be executed based on the condition, as they are updating the same memory location.
Intel Pentium Microprocessor – That has a core execution unit and two integer pipelines and floating-point pipeline with a dedicated adder, multiplier, and divider.
The Separate on-chip instruction code and data caches meet the memory demands of the execution units, with a branch target buffer augmenting the instruction cache for dynamic branch prediction.
The external interface includes separate addresses and a 64-bit data bus.
Pipeline – The pipeline has five stages.
They are prefetch, first decode, the second decode, execute, and write back.
The U and V pipeline have separate ALU’s Arithmetic Logic Unit is used for addition, subtraction, multiplication operations.
Resource Dependency – It occurs when two instructions write the results. that are read or written by another instruction.
Control Dependency – It occurs when the result of one instruction determines whether another instruction has to be executed or not.
Branch Prediction – This is a technique to predict the most likely set of instructions to be executed, and “prefetch” to make them available to the pipelines as and when they are referred.
The Pentium employs a Branch Target Buffer (BTB). which is an associative memory used to improve the performance if it takes the Branch Instructions.
Cache Organization – The Floating point unit supports common functions such as the computationally expensive divide function with hard-wired implementation, speeding up across the board.
Pentium floating-point pipeline consists of eight stages – They are Prefetch, First Decode, Second Decode, Operand Fetch, First Execute, Second Execute, Write Float, Error Reporting.
Register Stack Manipulation – The 8086 floating-point instruction set users the register file as a stack of eight registers. which the top of the stack (TOS) acts as an accumulator of the result.
Intel Pentium Processor is an entry-level processor developed based on X86 architecture like 32 bit is 4GB data or less than 4GB data and 64 bit is 8GB data or More than 8GB data. see more Intel Pentium Processor.
Today we know that we are using I3, I5, I7, I9 processor for the computer system. It’s a Xeon series processor. The Xeron is much faster than the atom and Celeron. processor.
These all are developed by Intel. we will see more processors in upcoming days. I mean “Intel” in the computer processor. Intel is improving the skill to build a new processor by using the front-end stack developer.
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